1. Field
Integrated circuit processing.
2. Description of Related Art
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send and/or receive signals external to the device(s). Common types of interconnections include copper and copper alloy interconnections (lines) coupled to individual devices, including other interconnections (lines) by interconnections through vias.
A typical method of forming an interconnection, particularly a copper interconnection, is a damascene process. A typical damascene process involves forming a via and an overlying trench in a dielectric to an underlying circuit device, such as a transistor or an interconnection. The via and trench are then lined with a barrier layer of a refractory material, such as titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), or tantalum nitride (TaN). The barrier layer serves, in one aspect, to inhibit the diffusion of the interconnection material that will subsequently be introduced in the via and trench into the dielectric. Next, an adhesion layer may be formed on the barrier layer to improve the adhesion of a subsequently formed conductive interconnection to the barrier layer or the via and/or trench. Suitable materials for an adhesion layer include titanium (Ti), tantalum (Ta) and ruthenium (Ru). Next, a suitable seed material is deposited on the walls of the via and trench. Suitable seed materials for the deposition of copper interconnection material include copper (Cu), nickel (Ni), cobalt (Co), and ruthenium (Ru). Next, interconnection material, such as copper, is introduced by electroplating in a sufficient amount to fill the via and trench and complete the interconnect structure. Once introduced, the interconnection structure may be planarized and a dielectric material (including an interlayer dielectric material) introduced over the interconnection structure to suitably isolate the structure.
As via and trench widths become smaller, the conductivity and fill ability of an interconnection may be changed. For example, physical vapor deposition (PVD) of a barrier layer or seed layer into a narrow via or trench is typically not conformal (i.e. non-uniform thickness of the via or trench). In addition, an overhang of the PVD-deposited material at an opening of the via or trench may pinch-off the via or trench and inhibit the ability to fill the via or trench with conductive material.
With respect to a seed layer, attempts to deposit a seed layer by chemical vapor deposition (CVD) often involve the use of an organometallic precursor (e.g., a copper ion complexed or otherwise bound to an organic moiety). The copper center of the organometallic precursor is then reduced with a reducing agent to form the seed layer. The organic moieties of the organometallic precursors for deposition of copper thin film, typically include fluorine. Even trace amounts of fluorine trapped or otherwise present in a copper seed layer may migrate toward the interconnect material or barrier layer and cause electromigration issues due to the formation of less adhesive interfaces and/or conductor contamination.